/*****************************************************************************
*    Ali Corp. All Rights Reserved. 2002 Copyright (C)
*
*    File:    sys_config.h
*
*    Description:    This file contains all system configuration switches and
*						parameter definations.
*    History:
*           Date            Athor        Version          Reason
*	    ============	=============	=========	=================
*	1.	Jan.18.2003       Justin Wu       Ver 0.1    Create file.
*	2.	Feb.10.2003		  Justin Wu       Ver 0.2    Update
*	3.  2003.2.13         Liu Lan         Ver 0.3    M3325 config
*****************************************************************************/

#ifndef _SYS_CONFIG_H_
#define _SYS_CONFIG_H_

#include <sys_define.h>

#define DB_VERSION			40
//#define PANEL_16515_VFD
//#define	PANEL_16312_VFD
/****************************************************************************
 * Section for SW configuration.
 ****************************************************************************/
#define COMBOUI
#define HDCP_IN_FLASH
#define HDCPKEY_CHUNK_ID (HDCPKEY_CHUNID_TYPE |0x0100)


//#define PRODUCT_SN_IN_FLASH
//#define PRODUCT_SN_CHUNK_ID		0x08F70100

#ifdef _DUAL_CPU_E_
	#define DUAL_CPU
#endif

#ifdef _HW_SECURITY_E_
	#define HW_SECURE_ENABLE    	// HW security enable
#endif

#define HDMI_CEC_ENABLE
#define PAN_INFO_ALIGN

//#define CI_PLUS_SUPPORT     //CI Plus maincode verify

#define SYS_PROJECT				SYS_DEFINE_NULL	/* Target project */
#define SYS_PROJECT_FE			PROJECT_FE_DVBS

#define SYS_VERSION_BL			"01.000.00"		/* Boot loader: %02d.%03d.%02d */
#define SYS_VERSION_SW			"00.000.00"		/* Software:    %02d.%03d.%02d */
#define SYS_VERSION_PL			"00.000.00"		/* Program list:%02d.%03d.%02d */

#define SYS_OS_MODULE			NO_OS			/* OS configuration */

#define SYS_MW_MODULE			SYS_DEFINE_NULL	/* MW configuration */

#define SYS_CA_MODULE			SYS_DEFINE_NULL	/* CA configuration */

#define SYS_EPG_MODULE			SYS_DEFINE_NULL	/* EPG configuration */

//#define DDR_POWER_CONTROL_ENABLE // use a GPIO to control the DDR power on/off
#ifdef DDR_POWER_CONTROL_ENABLE
	#define DDR_POWER_CTL_GPIO_POS		37		/* depends on board design */
	#define DDR_POWER_CTL_GPIO_POLAR	1		/* depends on board design */
#else
	#define DDR_POWER_CTL_GPIO_POS		0xffff	/* invalid GPIO */
	#define DDR_POWER_CTL_GPIO_POLAR	0
#endif


/****************************************************************************
 * Section for HW configuration, include bus configuration.
 ****************************************************************************/
/* customer loader build related */
//#define SYS_MAIN_BOARD			BOARD_M3327_GMI00
#define SYS_MAIN_BOARD			 BOARD_DB_M3602_02V01 // BOARD_S3602_DEMO  //BOARD_ATSC_DEMO_00
//#define C3041

/* makefile.cmd for LLD_PAN_XXX */
#define SYS_CHIP_MODULE			ALI_S3602		/* Chip configuration */

#define SYS_CPU_MODULE			CPU_MIPS24KE		/* CPU configuration */
#define SYS_CPU_ENDIAN			ENDIAN_LITTLE	/* CPU endian */

#define SYS_CHIP_CLOCK			27000000		/* Extarnal clock */
//#define SYS_CPU_CLOCK			396000000		/* CPU clock */
//#define SYS_CPU_CLOCK               (sys_ic_get_cpu_clock()*1000000)

#if (SYS_MAIN_BOARD == BOARD_S3602_DEMO)           //   4 ==  4M,  8 ==  8M,
#define SYS_SDRAM_SIZE			128	   // 16 == 16M, 32 == 32M,
#define SDRAM_BIT_MODE			32
#elif (SYS_MAIN_BOARD == BOARD_ATSC_DEMO_00)       // 64 == 64M, etc.     
#define SYS_SDRAM_SIZE			64
#define SDRAM_BIT_MODE			32
#elif (SYS_MAIN_BOARD == BOARD_DB_M3602_02V01)
#define SYS_SDRAM_SIZE			64
#define SDRAM_BIT_MODE			16
#elif (SYS_MAIN_BOARD == BOARD_DB_M3602_05V01)
#define SYS_SDRAM_SIZE			128
#define SDRAM_BIT_MODE			32
#endif								   

#define SYS_GPIO_MODULE			M3602F_GPIO		/* GPIO configuration */

#define SYS_I2C_MODULE			M6303I2C		/* I2C configuration */
#define SYS_I2C_SDA				SYS_DEFINE_NULL	/* I2C SDA GPIO pin number */
#define SYS_I2C_SCL				SYS_DEFINE_NULL	/* I2C SDL GPIO pin number */

#define SYS_PCI_MODULE			SYS_DEFINE_NULL	/* PCI configuration */

#define SYS_SCI_MODULE			UART16550		/* SCI configuration */


/*******Memory Mapping*******/
#if ( SYS_SDRAM_SIZE == 2 )
#define __MM_BUF_TOP_ADDR		0XA0200000
#define __MM_FB0_Y_LEN			0X65400
#define __MM_FB0_C_LEN			0X32C00
#define __MM_FB1_Y_LEN			0
#define __MM_FB1_C_LEN			0
#define __MM_FB2_Y_LEN			0
#define __MM_FB2_C_LEN			0
#define __MM_OSD_LEN			0
#define __MM_VBV_LEN			0X10000
#define __MM_DMX_SI_LEN			0
#define __MM_DMX_SI_TOTAL_LEN	(__MM_DMX_SI_LEN*12)
#define __MM_SI_VBV_OFFSET		0
#define __MM_DMX_DATA_LEN		0
#define __MM_DMX_PCR_LEN		0
#define __MM_DMX_AUDIO_LEN		0
#define __MM_DMX_VIDEO_LEN		0
#define __MM_DMX_AVP_LEN		(__MM_DMX_VIDEO_LEN+__MM_DMX_AUDIO_LEN+__MM_DMX_PCR_LEN)

#define __MM_FB0_Y_START_ADDR	((__MM_BUF_TOP_ADDR - __MM_FB0_Y_LEN)&0XFFFFFF00)
#define __MM_FB0_C_START_ADDR	((__MM_FB0_Y_START_ADDR - __MM_FB0_C_LEN)&0XFFFFFF00)
#define __MM_FB1_Y_START_ADDR	((__MM_FB0_C_START_ADDR - __MM_FB1_Y_LEN)&0XFFFFFF00)
#define __MM_FB1_C_START_ADDR	((__MM_FB1_Y_START_ADDR - __MM_FB1_C_LEN)&0XFFFFFF00)
#define __MM_FB2_Y_START_ADDR	((__MM_FB1_C_START_ADDR - __MM_FB2_Y_LEN)&0XFFFFFF00)
#define __MM_FB2_C_START_ADDR	((__MM_FB2_Y_START_ADDR - __MM_FB2_C_LEN)&0XFFFFFF00)
#define __MM_OSD_START_ADDR		((__MM_FB2_C_START_ADDR - __MM_OSD_LEN)&0XFFFFFFF0)
#define __MM_VBV_START_ADDR		((__MM_OSD_START_ADDR - __MM_VBV_LEN)&0XFFFFFF00)
#define __MM_DMX_AVP_START_ADDR	((__MM_VBV_START_ADDR - __MM_SI_VBV_OFFSET - __MM_DMX_DATA_LEN - __MM_DMX_AVP_LEN)&0XFFFFFFFC)
#define __MM_HEAP_TOP_ADDR		__MM_DMX_AVP_START_ADDR
#define __MM_MAF_START_ADDR		0XFFFFFFFF
#define __MM_DVW_START_ADDR		0XFFFFFFFF
#elif ( SYS_SDRAM_SIZE == 4 )
#define __MM_BUF_TOP_ADDR		0XA0400000
#define __MM_FB0_Y_LEN			0X65400
#define __MM_FB0_C_LEN			0X32C00
#define __MM_FB1_Y_LEN			0
#define __MM_FB1_C_LEN			0
#define __MM_FB2_Y_LEN			0
#define __MM_FB2_C_LEN			0
#define __MM_MAF_LEN			0
#define __MM_DVW_LEN			0
#define __MM_OSD_LEN			0
#define __MM_VBV_LEN			0X10000
#define __MM_DMX_SI_LEN			0
#define __MM_DMX_SI_TOTAL_LEN	(__MM_DMX_SI_LEN*28)
#define __MM_SI_VBV_OFFSET		0
#define __MM_DMX_DATA_LEN		0
#define __MM_DMX_PCR_LEN		0
#define __MM_DMX_AUDIO_LEN		0
#define __MM_DMX_VIDEO_LEN		0
#define __MM_DMX_AVP_LEN		(__MM_DMX_VIDEO_LEN+__MM_DMX_AUDIO_LEN+__MM_DMX_PCR_LEN)
#define __MM_TTX_BS_LEN			0
#define __MM_TTX_PB_LEN			0
#define __MM_SUB_BS_LEN			0
#define __MM_SUB_PB_LEN			0

#define __MM_FB0_Y_START_ADDR	((__MM_BUF_TOP_ADDR - __MM_FB0_Y_LEN)&0XFFFFFF00)
#define __MM_FB0_C_START_ADDR	((__MM_FB0_Y_START_ADDR - __MM_FB0_C_LEN)&0XFFFFFF00)
#define __MM_FB1_Y_START_ADDR	((__MM_FB0_C_START_ADDR - __MM_FB1_Y_LEN)&0XFFFFFF00)
#define __MM_FB1_C_START_ADDR	((__MM_FB1_Y_START_ADDR - __MM_FB1_C_LEN)&0XFFFFFF00)
#define __MM_FB2_Y_START_ADDR	((__MM_FB1_C_START_ADDR - __MM_FB2_Y_LEN)&0XFFFFFF00)
#define __MM_FB2_C_START_ADDR	((__MM_FB2_Y_START_ADDR - __MM_FB2_C_LEN)&0XFFFFFF00)
#define __MM_MAF_START_ADDR		((__MM_FB2_C_START_ADDR - __MM_MAF_LEN)&0XFFFFFC00)
#define __MM_DVW_START_ADDR		((__MM_MAF_START_ADDR - __MM_DVW_LEN)&0XFFFFFFF0)
#define __MM_OSD_START_ADDR		((__MM_DVW_START_ADDR - __MM_OSD_LEN)&0XFFFFFFF0)
#define __MM_VBV_START_ADDR		((__MM_OSD_START_ADDR - __MM_VBV_LEN)&0XFFFFFF00)
#define __MM_DMX_AVP_START_ADDR	((__MM_VBV_START_ADDR - __MM_SI_VBV_OFFSET - __MM_DMX_DATA_LEN - __MM_DMX_AVP_LEN)&0XFFFFFFFC)

#define __MM_TTX_BS_START_ADDR	__MM_FB2_C_START_ADDR
#define __MM_TTX_PB_START_ADDR	(__MM_TTX_BS_START_ADDR+__MM_TTX_BS_LEN)
#define __MM_SUB_BS_START_ADDR	__MM_DVW_START_ADDR
#define __MM_SUB_PB_START_ADDR	(__MM_SUB_BS_START_ADDR+__MM_SUB_BS_LEN)
#define __MM_HEAP_TOP_ADDR		__MM_DMX_AVP_START_ADDR
#elif(SYS_SDRAM_SIZE == 8)
#define __MM_BUF_TOP_ADDR		0XA0800000
#define __MM_FB0_Y_LEN			0X65400
#define __MM_FB0_C_LEN			0X32C00
#define __MM_FB1_Y_LEN			0
#define __MM_FB1_C_LEN			0
#define __MM_FB2_Y_LEN			0
#define __MM_FB2_C_LEN			0
#define __MM_MAF_LEN			0
#define __MM_DVW_LEN			0
#define __MM_OSD_LEN			0
#define __MM_VBV_LEN			0X10000
#define __MM_DMX_SI_LEN			0
#define __MM_DMX_SI_TOTAL_LEN	(__MM_DMX_SI_LEN*28)
#define __MM_SI_VBV_OFFSET		__MM_DMX_SI_TOTAL_LEN
#define __MM_DMX_DATA_LEN		0
#define __MM_DMX_PCR_LEN		0
#define __MM_DMX_AUDIO_LEN		0
#define __MM_DMX_VIDEO_LEN		0
#define __MM_DMX_AVP_LEN		(__MM_DMX_VIDEO_LEN+__MM_DMX_AUDIO_LEN+__MM_DMX_PCR_LEN)
#define __MM_TTX_BS_LEN			0
#define __MM_TTX_PB_LEN			0
#define __MM_SUB_BS_LEN			0
#define __MM_SUB_PB_LEN			0

#define __MM_FB0_Y_START_ADDR	((__MM_BUF_TOP_ADDR - __MM_FB0_Y_LEN)&0XFFFFFF00)
#define __MM_FB0_C_START_ADDR	((__MM_FB0_Y_START_ADDR - __MM_FB0_C_LEN)&0XFFFFFF00)
#define __MM_FB1_Y_START_ADDR	((__MM_FB0_C_START_ADDR - __MM_FB1_Y_LEN)&0XFFFFFF00)
#define __MM_FB1_C_START_ADDR	((__MM_FB1_Y_START_ADDR - __MM_FB1_C_LEN)&0XFFFFFF00)
#define __MM_FB2_Y_START_ADDR	((__MM_FB1_C_START_ADDR - __MM_FB2_Y_LEN)&0XFFFFFF00)
#define __MM_FB2_C_START_ADDR	((__MM_FB2_Y_START_ADDR - __MM_FB2_C_LEN)&0XFFFFFF00)
#define __MM_MAF_START_ADDR		((__MM_FB2_C_START_ADDR - __MM_MAF_LEN)&0XFFFFFC00)
#define __MM_DVW_START_ADDR		((__MM_MAF_START_ADDR - __MM_DVW_LEN)&0XFFFFFFF0)
#define __MM_OSD_START_ADDR		((__MM_DVW_START_ADDR - __MM_OSD_LEN)&0XFFFFFFF0)
#define __MM_VBV_START_ADDR		((__MM_OSD_START_ADDR - __MM_VBV_LEN)&0XFFFFFF00)
#define __MM_DMX_AVP_START_ADDR	((__MM_VBV_START_ADDR - __MM_SI_VBV_OFFSET - __MM_DMX_DATA_LEN - __MM_DMX_AVP_LEN)&0XFFFFFFFC)

#define __MM_TTX_BS_START_ADDR	((__MM_DMX_AVP_START_ADDR - __MM_TTX_BS_LEN)&0XFFFFFFFC)
#define __MM_TTX_PB_START_ADDR	((__MM_TTX_BS_START_ADDR - __MM_TTX_PB_LEN)&0XFFFFFFFC)
#define __MM_SUB_BS_START_ADDR	__MM_DVW_START_ADDR
#define __MM_SUB_PB_START_ADDR	(__MM_SUB_BS_START_ADDR+__MM_SUB_BS_LEN)
#define __MM_HEAP_TOP_ADDR		__MM_TTX_PB_START_ADDR
#elif(SYS_SDRAM_SIZE == 16) //( SYS_SDRAM_SIZE >= 16 )
#define __MM_BUF_TOP_ADDR		0XA1000000
#define __MM_FB0_Y_LEN			0X65400
#define __MM_FB0_C_LEN			0X32C00
#define __MM_FB1_Y_LEN			0
#define __MM_FB1_C_LEN			0
#define __MM_FB2_Y_LEN			0
#define __MM_FB2_C_LEN			0
#define __MM_MAF_LEN			0
#define __MM_DVW_LEN			0
#define __MM_OSD_LEN			0
#define __MM_VBV_LEN			0X10000
#define __MM_DMX_SI_LEN			0
#define __MM_DMX_SI_TOTAL_LEN	(__MM_DMX_SI_LEN*28)
#define __MM_SI_VBV_OFFSET		__MM_DMX_SI_TOTAL_LEN
#define __MM_DMX_DATA_LEN		0
#define __MM_DMX_PCR_LEN		0
#define __MM_DMX_AUDIO_LEN		0
#define __MM_DMX_VIDEO_LEN		0
#define __MM_DMX_AVP_LEN		(__MM_DMX_VIDEO_LEN+__MM_DMX_AUDIO_LEN+__MM_DMX_PCR_LEN)
#define __MM_TTX_BS_LEN			0
#define __MM_TTX_PB_LEN			0
#define __MM_SUB_BS_LEN			0
#define __MM_SUB_PB_LEN			0

#define __MM_FB0_Y_START_ADDR	((__MM_BUF_TOP_ADDR - __MM_FB0_Y_LEN)&0XFFFFFF00)
#define __MM_FB0_C_START_ADDR	((__MM_FB0_Y_START_ADDR - __MM_FB0_C_LEN)&0XFFFFFF00)
#define __MM_FB1_Y_START_ADDR	((__MM_FB0_C_START_ADDR - __MM_FB1_Y_LEN)&0XFFFFFF00)
#define __MM_FB1_C_START_ADDR	((__MM_FB1_Y_START_ADDR - __MM_FB1_C_LEN)&0XFFFFFF00)
#define __MM_FB2_Y_START_ADDR	((__MM_FB1_C_START_ADDR - __MM_FB2_Y_LEN)&0XFFFFFF00)
#define __MM_FB2_C_START_ADDR	((__MM_FB2_Y_START_ADDR - __MM_FB2_C_LEN)&0XFFFFFF00)
#define __MM_MAF_START_ADDR		((__MM_FB2_C_START_ADDR - __MM_MAF_LEN)&0XFFFFFC00)
#define __MM_DVW_START_ADDR		((__MM_MAF_START_ADDR - __MM_DVW_LEN)&0XFFFFFFF0)
#define __MM_OSD_START_ADDR		((__MM_DVW_START_ADDR - __MM_OSD_LEN)&0XFFFFFFF0)
#define __MM_VBV_START_ADDR		((__MM_OSD_START_ADDR - __MM_VBV_LEN)&0XFFFFFF00)
#define __MM_DMX_AVP_START_ADDR	((__MM_VBV_START_ADDR - __MM_SI_VBV_OFFSET - __MM_DMX_DATA_LEN - __MM_DMX_AVP_LEN)&0XFFFFFFFC)

#define __MM_TTX_BS_START_ADDR	((__MM_DMX_AVP_START_ADDR - __MM_TTX_BS_LEN)&0XFFFFFFFC)
#define __MM_TTX_PB_START_ADDR	((__MM_TTX_BS_START_ADDR - __MM_TTX_PB_LEN)&0XFFFFFFFC)
#define __MM_SUB_BS_START_ADDR	__MM_DVW_START_ADDR
#define __MM_SUB_PB_START_ADDR	(__MM_SUB_BS_START_ADDR+__MM_SUB_BS_LEN)
#define __MM_HEAP_TOP_ADDR		__MM_TTX_PB_START_ADDR
#elif (SYS_SDRAM_SIZE >= 32) //( SYS_SDRAM_SIZE = 32 )
#define __MM_BUF_TOP_ADDR		0XA4000000
#define __MM_FB0_Y_LEN			0X65400
#define __MM_FB0_C_LEN			0X32C00
#define __MM_FB1_Y_LEN			0
#define __MM_FB1_C_LEN			0
#define __MM_FB2_Y_LEN			0
#define __MM_FB2_C_LEN			0
#define __MM_MAF_LEN			0
#define __MM_DVW_LEN			0
#define __MM_OSD_LEN			0
#define __MM_VBV_LEN			0X10000
#define __MM_DMX_SI_LEN			0
#define __MM_DMX_SI_TOTAL_LEN	(__MM_DMX_SI_LEN*28)
#define __MM_SI_VBV_OFFSET		__MM_DMX_SI_TOTAL_LEN
#define __MM_DMX_DATA_LEN		0
#define __MM_DMX_PCR_LEN		0
#define __MM_DMX_AUDIO_LEN		0
#define __MM_DMX_VIDEO_LEN		0
#define __MM_DMX_AVP_LEN		(__MM_DMX_VIDEO_LEN+__MM_DMX_AUDIO_LEN+__MM_DMX_PCR_LEN)
#define __MM_TTX_BS_LEN			0
#define __MM_TTX_PB_LEN			0
#define __MM_SUB_BS_LEN			0
#define __MM_SUB_PB_LEN			0

#define __MM_FB0_Y_START_ADDR	((__MM_BUF_TOP_ADDR - __MM_FB0_Y_LEN)&0XFFFFFF00)
#define __MM_FB0_C_START_ADDR	((__MM_FB0_Y_START_ADDR - __MM_FB0_C_LEN)&0XFFFFFF00)
#define __MM_FB1_Y_START_ADDR	((__MM_FB0_C_START_ADDR - __MM_FB1_Y_LEN)&0XFFFFFF00)
#define __MM_FB1_C_START_ADDR	((__MM_FB1_Y_START_ADDR - __MM_FB1_C_LEN)&0XFFFFFF00)
#define __MM_FB2_Y_START_ADDR	((__MM_FB1_C_START_ADDR - __MM_FB2_Y_LEN)&0XFFFFFF00)
#define __MM_FB2_C_START_ADDR	((__MM_FB2_Y_START_ADDR - __MM_FB2_C_LEN)&0XFFFFFF00)
#define __MM_MAF_START_ADDR		((__MM_FB2_C_START_ADDR - __MM_MAF_LEN)&0XFFFFFC00)
#define __MM_DVW_START_ADDR		((__MM_MAF_START_ADDR - __MM_DVW_LEN)&0XFFFFFFF0)
#define __MM_OSD_START_ADDR		((__MM_DVW_START_ADDR - __MM_OSD_LEN)&0XFFFFFFF0)
#define __MM_VBV_START_ADDR		((__MM_OSD_START_ADDR - __MM_VBV_LEN)&0XFFFFFF00)
#define __MM_DMX_AVP_START_ADDR	((__MM_VBV_START_ADDR - __MM_SI_VBV_OFFSET - __MM_DMX_DATA_LEN - __MM_DMX_AVP_LEN)&0XFFFFFFFC)

#define __MM_TTX_BS_START_ADDR	((__MM_DMX_AVP_START_ADDR - __MM_TTX_BS_LEN)&0XFFFFFFFC)
#define __MM_TTX_PB_START_ADDR	((__MM_TTX_BS_START_ADDR - __MM_TTX_PB_LEN)&0XFFFFFFFC)
#define __MM_SUB_BS_START_ADDR	__MM_DVW_START_ADDR
#define __MM_SUB_PB_START_ADDR	(__MM_SUB_BS_START_ADDR+__MM_SUB_BS_LEN)
#define __MM_HEAP_TOP_ADDR		__MM_TTX_PB_START_ADDR
#endif

/************** common data define ****************/
#ifndef DISABLE_PRESET_CLOCK
#if (SYS_CHIP_MODULE == ALI_M3327C && SYS_SDRAM_SIZE == 2)
#define SYS_COMMON_DATA_BASE_ADDR               0xbfc0fe80
#define SYS_COMMON_DATA_BASE_ADDR               0xbfc0fe80
#define SYS_DEFAULT_CPU_CLOCK_OFFSET                    0x00
#define SYS_DEFAULT_MEM_CLOCK_OFFSET                    0x01
#define SYS_DEFAULT_MEM_READ_CLOCK_DELAY_CHAIN_OFFSET   0x02
#define SYS_DEFAULT_MEM_CLOCK_TREE_DELAY_CHAIN_OFFSET   0x03

#define SYS_CPU_CLOCK_OFFSET                    		0x60
#define SYS_MEM_CLOCK_OFFSET                  			0x61
#define SYS_MEM_READ_CLOCK_DELAY_CHAIN_OFFSET   		0x62
#define SYS_MEM_CLOCK_TREE_DELAY_CHAIN_OFFSET   		0x63
#endif
#endif


/****************************************************************************
 * Section for HLD configuration.
 ****************************************************************************/


/****************************************************************************
 * Section for LLD configuration.
 ****************************************************************************/
#define SYS_FLASH_MODULE        AM29800B		/* Flash configuration */
//#define SYS_FLASH_BASE_ADDR		0xbfc00000		/* Flash base address */
#define SYS_FLASH_BASE_ADDR		0xafc00000		/* Flash base address */
#define SYS_FLASH_SIZE			0x200000		/* Flash size, in byte */

#define SYS_EEPROM_MODULE		SYS_DEFINE_NULL	/* EEPROM configuration */
#define SYS_EEPROM_BASE_ADDR	0xA0			/* EEPROM base address */
#define SYS_EEPROM_SIZE			1024			/* EEPROM size, in byte */

#define SYS_NET_MOUDLE			SYS_DEFINE_NULL	/* Net configuration */

#define SYS_DMX_MODULE			SYS_DEFINE_NULL	/* Demux configuration */

#define SYS_TUN_MODULE			SYS_DEFINE_NULL	/* Tuner configuration */
#define SYS_TUN_BASE_ADDR		SYS_DEFINE_NULL	/* Tuner device address */

#define SYS_DEM_MODULE			SYS_DEFINE_NULL	/* Demodulator configuration */
#define SYS_DEM_BASE_ADDR		SYS_DEFINE_NULL	/* Demodulator device address */

#define SYS_RFM_MODULE			SYS_DEFINE_NULL	/* RF modulator configuration */
#define SYS_RFM_BASE_ADDR		SYS_DEFINE_NULL	/* RF modulator device address */

#define SYS_IRP_MOUDLE			ROCK00 //GMI_00			/* IR Pad configuration */
//#define SYS_PAN_MOUDLE			GMI_PAN_SL65
#define SYS_PAN_MOUDLE			GMI_PAN_SL35

#define PANEL_DISPLAY

#define LOGO_ID					0x02FD0100

#define STANDBY_SUSPEND				0
#define STANDBY_SHOW_PANEL			1
#define STANDBY_PANEL_SHOW_TIMER	2
#define STANDBY_PANEL_SHOW_OFF		3
#define STANDBY_PANEL_SHOW_BLANK	4
#define STANDBY_ACTION				STANDBY_SHOW_PANEL

#define	STANDBY_PANEL_SHOW_WAHT	STANDBY_PANEL_SHOW_TIMER//STANDBY_PANEL_SHOW_TIMER
#define IRP_KEY_STANDBY			0x807fc03f
#define IRP_KEY_STANDBY2		0x60df708f

#if (SYS_MAIN_BOARD == BOARD_DB_M3602_02V01)
#ifdef PANEL_16515_VFD
#define PAN_KEY_STANDBY			0xFFFF0004
#else
#define PAN_KEY_STANDBY			0xFFFF0008
#endif
#else
#define PAN_KEY_STANDBY			0xffff0001
#endif

#ifdef PANEL_DISPLAY

#define DEMO_RST_GPIO_NUM           127  // no GPIO for nim reset
#define QAM_INT_GPIO_NUM			  6

#define FP_LOCK_GPIO_NUM            127
#define FP_STANDBY_GPIO_NUM         127
#define FP_CLOCK_GPIO_NUM           127
#define FP_DATA_GPIO_NUM            127
#define FP_KEY1_GPIO_NUM            127
#define FP_COM1_GPIO_NUM            127
#define FP_COM2_GPIO_NUM            127
#define FP_COM3_GPIO_NUM            127
#define FP_COM4_GPIO_NUM            127
#endif
//#define GUNZIP_SUPPORT
//#define TRANSFER_FORMAT2_SUPPORT

#ifdef _EROM_E_
#define ENABLE_EROM
#endif
#ifdef _MULTI_SECTION_E
#define SUPPORT_MULTI_SECTION
#endif

#define ENABLE_SERIAL_FLASH
//#define SYS_SFLASH_FAST_READ_SUPPORT

#define GPIO_MUTE	0
#define SCART_MUTE	1

#if (SYS_MAIN_BOARD == BOARD_S3602_DEMO || SYS_MAIN_BOARD == BOARD_ATSC_DEMO_00)
#define SYS_MUTE_MODE				GPIO_MUTE
#define MUTE_CIRCUIT_GPIO_NUM		67

#elif (SYS_MAIN_BOARD == BOARD_DB_M3602_02V01)
#define SYS_MUTE_MODE				GPIO_MUTE
# if (SYS_MUTE_MODE == GPIO_MUTE)
#  define MUTE_CIRCUIT_GPIO_NUM		76
# else
#  define SCART_POWER_DOWN_GPIO_NUM	70
# endif

#elif (SYS_MAIN_BOARD == BOARD_DB_M3602_05V01)
#define SYS_MUTE_MODE				GPIO_MUTE
#define MUTE_CIRCUIT_GPIO_NUM		69
#elif (SYS_MAIN_BOARD == BOARD_DB_M3606_01V01)
#define SYS_MUTE_MODE				127
#define MUTE_CIRCUIT_GPIO_NUM		127
#define SCART_POWER_DOWN_GPIO_NUM	127
#ifdef C3041
#define FP_CS_GPIO_NUM				8
#define FP_CLOCK_GPIO_NUM			37
#define FP_DATA_GPIO_NUM			9
#endif
#endif
#ifdef HW_SECURE_ENABLE
#define __MM_SHARED_MEM_LEN  256
#else
#define __MM_SHARED_MEM_LEN  512
#endif
#define __MM_PRIVATE_LEN    (0x01000000-__MM_SHARED_MEM_LEN)

#define __MM_TOP_ADDR		(0xa8000000)
#define __MM_SHARE_BASE_ADDR (__MM_TOP_ADDR-__MM_SHARED_MEM_LEN)
#define __MM_PRIVATE_TOP_ADDR (__MM_SHARE_BASE_ADDR)
#define __MM_PRIVATE_ADDR		(__MM_PRIVATE_TOP_ADDR - __MM_PRIVATE_LEN)
#endif	/* _SYS_CONFIG_H_ */
